Delay-Locked Loops (“DLLs”) and Phase-Locked Loops (“PLLs”) are well-known examples of synchronization circuits which may be used for obtaining a lock to an externally provided signal, such as synchronizing an internal clock signal with an externally provided clock signal. However, a PLL may have jitter accumulation caused by phase noise inside the voltage-controlled oscillator of the PLL, and thus a DLL, which has no jitter accumulation, may be a preferable alternative over a PLL for digital Very-Large-Scale Integration (“VLSI”) circuits.
However, input jitter of a clock signal or intrinsic DLL static offset may negatively impact performance of a lock detector of a DLL. For example, in a DLL there is no jitter accumulation, even when the DLL is out of lock, and thus a conventional lock detector may not be able to delineate between an actual out-of-lock condition and a false out of lock condition (“false alarm”). A false alarm may be caused by jitter or intrinsic static DLL offset or a combination thereof.
Accordingly, it would be desirable and useful to provide a lock detector that is less likely to produce a false alarm than a conventional lock detector.